• They require too many page table entries and concomitantly, too many TLB entries. (Solving this problem requires hardware features that some processors lack.)
• Inefficient access to disk—many head motions needed where one might otherwise do. (The Keykos space bank tried to allocate disk-contiguous pages on successive calls.)

In Keykos the natural hardware independent solution would be 64K pages. These would fit naturally anywhere a LSS=4 node would fit.

Alternatively one could make pages of a size that naturally fit some disk architecture or the TLB details of some particular CPU. In this case those few Keykos applications that built memory trees would have to adapt to current processor.

These ideas assume that big pages in RAM are needed in just those cases where big pages are needed on disk. If a kernel were ported to a machine with TBL entries for large RAM pages then the kernel could be taught to cache some segments using only large RAM pages. A power of 16 is not required for that; a power of 2 is. The only external spec change would be to tell the kernel when and for which segments to do this. With no kernel spec changes the kernel could indeed do this adaptively. This would work on some SPARC’s.

If the cost of leaf nodes in the memory tree becomes an issue it is possible to invent a 64K page on disk even while the TLB maps it in 4K pages. The kernel might bring it to RAM piecemeal without change to external specs.