8b/10b encoding commonly used to code arbitrary bit streams into DC balanced light streams have several codes left over. We adopt one of these codes to mean end of block and look for a new DRAM buffer. These stream marks are guaranteed to occur at least every 2¹⁹ bits but not more often than 2¹⁸ bits. They can be limited to occurring on 2⁹ (or some such) byte boundaries if that helps hardware design. When we look for a new DRAM buffer we look for a recurrent time slot in a box of DRAMs and a bank therein where we can open a line in each of the DRAMs. Those lines will stay open until the next mark. The non-blocking cross bar such as that described above, can be reprogrammed to accommodate a new permutation and the signals can be routed to their new home. There are two cases in DSR, big packets that occupy full blocks and small packets that share but do not span blocks. Headers of big packets are delivered to a separate DRAM manifest queue (bill of lading) along with information to locate the packet payload. The shared fiber blocks go intact to a DRAM buffer and a note is delivered to the manifest queue.