In conjunction with these ideas:
Format C:
I presume a bit map with a bit per 64KB DRAM buffer and that the hardware is able to find a bit there and turn it off as it needs to deposit a new payload in DRAM. I think that modern DRAMs have a large ratio of capacity to bandwidth for our purposes and that we have ample capacity to afford 64KB buffers even to short packets. If there is backward error control, which I presume, then the bit cannot be turned off until correct receipt is acknowledged. The software is responsible for freeing these buffers and updating the bitmap. If small packets must loiter, they can be temporarily moved from their large buffer.
Format D
No bit map required. A CPU activity is required to move loitering payloads out of the way.
I presume that the path from fiber to DRAM is not highly switched whereas the path from DRAM to fiber is. Such switching is very expensive and need not be duplicated. See this. Consequently a particular fiber is able only to deposit incoming payload to a particular portion of real DRAM.

This DRAM might or might not be addressable by the CPU. The CPU will need access to that DRAM but seldom. Here are some reasons: