IBM 360 & 370 Interrupt Logic

There is a register called the PSW (Program Status Word) that includes:

the program counter,
6 interrupt enable bits,
a memory map ON-OFF control bit,
the privileged mode bit,
a few more bits associated with the program visible state.

Some version of the Principles of Operation once said: In normal processing the machine repetitively does:

Consider whether any of the 6 interrupt sources are both enabled and pending. If so one such source is chosen depending on an architecturally decreed priority. That interrupt is serviced.
Otherwise an instruction at the designated location is fetched and performed.

To service an interrupt:

The current PSW is stored in a real memory location depending on which of the 6 sources the interrupt is due to,
Another PSW is loaded from another real memory location depending on which of the 6 sources the interrupt is due to,
Normal processing is resumed.

Having restored register values there was a privileged instruction LPSW with which the interrupt routine could return. Note that several interrupts may occur without intervening executed instructions. Also much latitude in choosing interrupt priority was available by specifying the 36 enabling bits.

I remark on this design not so much because it is good, but because this short description gave me confidence that I could design a kernel without danger that I misunderstood how interrupts worked. For instance the description made it clear that it was feasible for all the privileged code to run unmapped. On several other architectures it took many many hours of manual reading to achieve that confidence; and sometimes then I was still not sure. This bears on avoiding the Reserved Address Plan.

The 370 kernels I am familiar with all left the 6 locations from which the hardware fetched PSWs fixed. They were set only as the kernel loaded.