AMD has their own “Pacifica” scheme which I have not studied closely. As of 2006 June, these hardware features are introduced in chapter 15 of the AMD64 Architecture Programmer's Manual Volume 2: System Programming.

There are many differences between Intel's Vanderpool and AMD’s Pacifica. Both companies have abandoned these preliminary project code names.

AMD touts their tagged TLB as a security feature, or at least a feature that enhances the performance of a VM kernel. I presume that they have built it so that other sorts of kernels can get the advantages that most CPUs have offered for decades now.

SKINIT is a new instruction in support of attestation. It is a strategic Google hook too.

AMD’s SVM mode has much the flavor of IBM’s SIE instruction. That is the state of an XA machine (that followed IBM’s 370 about 1980) after executing the SIE instruction, is analogous to the SVM mode.