This is a description of the implementation of the PTLB instruction on the Amdahl V8 which was an IBM 370 compatible computer of the 1970’s. A TLB is a sort of cache, kept by and used by the hardware, of values kept in page tables in RAM. When the software changes those tables it is obligated to purge the TLB so that the new page table values will take effect. The privileged PTLB instruction provides this notification to the hardware.
The Amdahl TLB was not fully associative and many sequential TLB cycles were required to accomplish the purge. The following hardware trick usually allowed the CPU to continue execution as this sequence of cycles proceeded concurrently and at low priority. There was a flip flop M that was toggled for each PTLB. Each TLB entry had a new P bit which was a copy of M when the entry was made. No TLB entry was usable unless its P bit matched M.
When a PTLB was issued M was flipped which caused all currently active entries to fail and thus the TLB behaved as if it had been purged. The hardware immediately began a low priority sequential pass over the TLB purging those entries of the previous regime but leaving values from the new regime in place. The processor continued executing instructions in the mean-time and could cause new entries to be made which would not be impacted by the asynchronous purging because its P value protected it.
If a new PTLB were issued before the process was finished the machine would stall; only entries from two regimes were allowed in the TLB at one time. This put a premium on avoiding PTLBs close in time. Some OS kernels ran unmapped and the PTLB function could postponed until just before restarting mapped user mode code whereupon the PTLB function would be initiated if a hardware bit had been set by an issued PTLB. PTLB sweeps were thus limited to one per map change.