In the early 60’s IBM produced a large computer called the “Harvest” for the NSA. I recall here the memory bus for the Harvest because it allocated bus cycles to competing bus users in a clever way. There may be ideas that can be used in our agoric computing projects.
The clock cycle for the whole machine was 300 ns, which was about twice the diameter of the machine. There were two kinds of core memory. There were six boxes of 2100 ns core, each with 128KB and each the size of a refrigerator, and two boxes of 1200 ns memory boxes each of 32KB. Both kinds of memory used 72 bits words which included ECC. Addressing was to the bit. There was one shared address bus and one shared 72 bit data bus. The large memory required the data bus 5 cycles after using the address bus and the fast memory required the data bus 4 cycles after using the address bus.
There were seven clients that needed direct access to memory, two for the CPU (instruction & data), One for the multiplexer of all of the slow channels, one for a fast channel, and three for each of the special data access units that fetched and stored the data when the machine was behaving as a non-von Neuman computer, which was its main fame.
On each clock cycle each client would determine which, if any, memory box it needed. If that box were not already occupied and the required future data bus slot was not already scheduled, then that client would bid for acquiring the address bus on the next cycle. Among the bidding clients needing idle memory boxes, the one with highest priority would be allocated the address bus and the future data bus cycle would be reserved. I do not recall whether one client had different priorities at different times but some data channel mechanisms would bid at different priorities depending on whether it was near overrun or under-run. Perhaps Mel Pirtle did this first for the SDS 940.
The IBM 701 had to refresh each of its Williams tube memory location about every 100 ms. It would normally usurp every 5th memory cycle which generally meant that the program lost 12 microseconds of headway. During a multiplication or division, there were about 30 unused memory cycles. The refresh logic used all of these and “got ahead of schedule”. The refresh logic would thus cease usurping memory for a period following a multiply or divide.
The Harvest had a program selectable mode called the “memory distribution mode” which paired some memory boxes so as to have the same physical addresses. In that mode some addresses would refer to two distinct places in real core, and in distinct memory boxes. In this mode reads would go to a box that was not busy if they were not both busy. Some sorts of memory updates would also choose the non-busy box as well. The otherwise standard Harvest memory boxes were augmented to perform a few simple operations such as add to memory, increment memory, ‘or’ to memory. In memory distribution mode the non busy box was chosen. This was efficient for building histograms, for instance and at the end of data generation the program would turn off the mode and combine the two sets of counts.
There may be ideas here for packet scheduling.
See this for some modern memory bus practice. This is a good survey of the 2007 memory art.