Memory mapping reminds me at first of the PowerPC. The top three virtual address bits index into one of eight Region Registers which supplies a Region ID (RID) which is from 18 to 24 bits depending on the implementation. The RID supplants the top three bits in the TLB. The region is the unit of sharing if you want good TLB efficiently. There is considerable variety on how regions are mapped. Page table size and page table entry size are both a properties of the region.
IBM's 370 map kept TLB entries from several spaces simultaneously by tagging each entry with an identifier of the address of their top level map. IBM called this feature the “STO STACK”.
Below is a quotation from the beginning of volume 2, section 4 of the manual that impacts the meaning of various other parts of the hardware map description:
A Virtual Hash Page Table (VHPT) is designed to augment the performance of the TLB. The VHPT is an extension of the processor's TLB that resides in memory and can be automatically searched by the processor. A particular operating system page table format is not dictated. However, the VHPT is designed to mesh with two common translation structures: the virtual linear page table and hashed page table. Enabling of the VHPT and the size of the VHPT are completely under software control.This is an important paragraph for otherwise talk of “virtual linear page tables” may lead one to think that it is a hardware feature. It misled me for a while. To be fair it did appear at the beginning of the mapping section. My little essay on such a feature was written thinking that IA64 had some such hardware feature.
If only DCR (pdf 2.43) defined bit 36 and 17 then we could turn off mapping upon entry to kernel, and escape the RAP.