Can interrupts be interrupted? The short answer is yes. Every system but one that I know, provides for a simple priority among interrupts. Interrupt sources are put into categories and a simple ordering is established among those categories. An exogenous interrupt signal of one level causes an interrupt only if the ‘current processing level’ is greater. Interrupts remain pending until the current processing level is greater than that of the pending interrupt. When an interrupt returns the current processing level is restored along with the rest of the machine state of the interrupted code. When an interrupt happens the current processing level becomes that of the level of the interrupt category.

Here is how the IBM 360 and several descendants managed this in detail. The prime magic of the 360-370 page zero interrupt design is the following: Exogenous interrupt sources are somewhat arbitrarily divided into 5 groups. A program status word (PSW) value has a 5 bit mask, one bit per group. The PSW includes the current instruction address. Some particular PSW is in control of the machine as it executes instructions. For each of the 5 interrupt classes, there is a pair of PSW size slots, OldOPSW and NewPSW, in page zero defined by hardware architecture. Before execution of an instruction (executions unit) the hardware looks for pending interrupt signals. If for some pending interrupt the corresponding mask bit in the current PSW is on, then the current PSW is stored in the first slot of the pair associated with that interrupt, and the NewPSW in the other slot of the pair becomes the current PSW. After the PSW swap the pending interrupts are examined again. If another interrupt is due, no instructions are executed. There was an architected priority for interrupts that arrived during an instruction but the masks allowed the OS to reorder priority.

This was the entire interrupt and interrupt masking mechanism. With it you could control the effective priority of interrupts. Later machines also had a special register with a per IO-channel mask bit.

The software system is thus in a position to establish the ranking of interrupts. The software is thus in a position to define the ordering by preparing the 5 new PSW mask values. I those masks are 

11111
11110
11100
11000
10000
then a simple ordering is established. This hardware supports 120 = 5! different simple orderings, some of which do not make sense by nature of the hardware assigned categories. Endogenous interrupts (divide by zero and such) always perform the PSW swap before any other operation but the new PSW may have few interrupt mask bits.

This hardware was simpler and more flexible that designs that I had seen before. It is simpler but possibly less flexible than I have seen since.