I have not learned whether a virtual machine constructed upon these hardware features, can have these features.
Section 2 is mainly a description of the virtual machine and how it is created. It is useful to many as an introduction and also to establish Intel’s terminology.
Sec 2.5.1 introduces the phrase “DMA-remapping hardware” which seems to match my notion of an IOMMU. That hardware consults the page tables defined for the CPU’s memory map.
Sec 2.5.2.1 speaks of “interrupt-remapping hardware”. I worry. Indeed they must be remapped.
Sec 2.5.2.2 is out of place. At least it presumes much more PCIe knowledge than it should.
Sec 3.1: “For details, refer to the Process Address Space ID (PASID) Capability in the PCI-Express specifications.” Hmm. x
We must learn who is able to submit a ‘Requests without address-space-identifier’ for those bypass the IOMMU. Googling “Requests without address-space-identifier” yields mostly pages in Chinese.
Clues from Graphics Manual. I have the impression that the device (endpoint) is responsible for remembering whether it has the authority to issue these requests and thus write on the running kernel. Also older devices may not have the smarts to distinguish.
Sec 3.4.1: begins “Each inbound request appearing at the address-translation hardware is required to identify the device originating the request.”. This puts the burden of correctly identifying the request source on the PCIe system.