I was once reading the comments in the micro code listings of the IBM 370 158. There was described this interesting scheme for error control in the volatile storage for the microcode.

I don’t recall the number of bits in the micro instruction — it was not a power of 2. Each instruction carried even parity but there was no assigned parity bit. The nature of the meanings of the micro code bits ensured that there were typically several bits whose values did not impact the meaning or timing of the micro op. The assembler knew enough about the semantics to find these bits and adjust them to produce even parity in each instruction.

The micro code memory was divided into 128 instruction blocks and the exclusive or of the instructions in a block was also zero. I think that the assembler could usually manage to use all the instructions of a block as well, but this may not have been the case. When a parity error was detected in the instruction it could be reconstituted as the exclusive or of the 127 remaining instructions of the block.