I have learned several interesting things recently from visiting the Rambus Inc. site.
Each memory chip built to that plan has 16 data leads each able to move data at 800 MHz.
There is sophisticated clocking and transmission line discipline to make things work.
Probably no current memory chips can sustain that rate for more than the nominal burst of 128 bits.
The bus components are phased however and just a few chips may be able to saturate the data bus.
The protocol also allows a single chip to begin a transaction before another has finished on the same chip.
Notable in the clear presentation is lack of information sufficient to build either memory chips or bus controllers.
Rambus Inc. sells VHDL logic to implement bus drivers and I would guess that chip manufactures pay for the information and rights to produce such ships.