This idea may be infeasible or very expensive to implement. The notion serves to define what I think a Quadrature Heterodyne does. It might serve to test ideas and designs thru simulation. The logic I speculate on here needs to be hardware, either analog or digital; software is too slow except for exploratory purposes.

Using the parameter names given here we assume that 1 ≤ k = fd2−n ≤ 16. k is the number of intermediate frequency cycles that occur during one sample period. We choose f to make k an integer. Assume that we executed the following code regularly with frequency 4f:

`a += antenna; {samp t = -a; a = b; b = c; c = d; d = t;}`
After every 4k of these events we send the complex number (a−c, b−d) to memory and reset a, b, c and d. These are the values said elsewhere to constitute the heterodyne yield. a, b, c and d are fixed point numbers each big enough to hold k times the largest fixed point antenna reading.

We thus sample at twice the Nyquist rate.

I saw the following idea for a fast A to D converter about 1960. Imagine a systolic array of about 4 to 6 of the following devices. The array need not be clocked. Each device inputs one analog signal Si whose level is between 0 and 1. Each device outputs a like output signal So, and a bit as well.
```So = if Si<1/2 then 1-2Si else 2Si-1
bo = Si<1/2```
Note that So is a continuous function of Si and can presumably be produced by a diode and amplifier. The output bits are unclocked but if we pick up these bits from the systolic array at times characteristic of the innate time delay thru the array, then we gather a Gray coded binary value for the signal. As a value changes by a small amount, at most one bit of its gray code changes. I suspect that this systolic array must actually be clocked. I am well beyond my depth here. There is add logic for adding Gray coded binary numbers. Certainly if the adds are done in ordinary binary they must be clocked.

A little thought shows that this logic is trivially parallelized except for the discretization of the signal from the antenna. This is the same sort of problem solved by circuits which grab 10GHz bit streams from optical fibers. If turbo codes are used there then even the AD logic would come from fiber practice.

To be entirely concrete we suppose that we have 16 digital samples, a, ... a, of 5 bits each, delivered each clock cycle to the 1 GHz clocked digital domain. The samples are real and equally spaced in time (62.5 ps each). The following calculation is equivalent to the above but expressed so as to be naturally parallel. For i = 0 and 1:
`a2[i] = a[i] + a[i+4] + a[i+8] + a[i+12] - (a[i+2] + a[i+6] + a[i+10] + a[i+14])`
(a2, a2) now form the complex input to the FFT. They are 9 bits each for now. When we have collected 220 such inputs, the CPU computes their fft. The next 220 inputs will arrive long before we have completed the fft. We will presumably drop those; we are sampling the spectrum not capturing it all; we are sipping from a fire hose.

We plant an artificial 20 kHz AM audio band of in white noise 20 times as strong. We modulate that AM carrier with 10 kHz white noise called g. We fabricate g every 213 ns as if the signal from the microphone were sampled at about 12 kHz. We need 27 = 128 samples of g. We must fabricate 224 samples for the modulated AM signal.

Parameter values: n = 20; f = 4GHz; b = 9; d = 1.048576 ms = 220 ns.
This assumes a 1 GHz digital clock. A 20 kHz band at a 3 GHz frequency is certainly unusual.