The cache that we discuss here is a hardware mechanism that remembers a subset of the contents of RAM. The cache is faster than RAM and thus speeds computing. The cache contents is in quanta of lines (about 32 bytes) and each line is associated with an entry in some sort of associative memory called the tag memory. The tag for a line identifies the place in RAM that the line belongs.

Most current and past computers with caches have used real caches where the tags are real address of the corresponding line. The virtual cache, by contrast, identifies lines by virtual address. In this context “virtual” is peculiar. Unlike most virtual things a virtual cache is just as real as a ‘real cache’. It is virtual only in identifying lines by virtual address. It would seem that when the kernel switches address spaces that the cache must be flushed. This is to avoid the confusion in the cache between data for distinct virtual address spaces.

Perhaps not.

The tag could well include a context identifier which would thus discriminate between the same virtual address in two spaces. There is yet the alias problem however. There are a variety of reasons to map distinct virtual addresses to the same real address. Here is one. Stores at one virtual address must appear promptly at the other. Real caches provide this function with no extra effort. A virtual cache may hold distinct lines for the same real line and these lines in the cache may hold different data. This is bad.

Jonathan Shapiro has been involved with the design of virtual caches and tells me that some designs counter this problem by ensuring that two such cache lines would be constrained to occupy the same physical location in the cache, thus precluding conflicting cache lines.

This would ensure that access to virtual address X would cause other virtual addresses in the cache mapping to the same real address to be flushed in time to make the two virtual addresses effectively hold the same data.

This would seem to me to mean that the capacity of the cache cannot exceed one page. First level caches are typically larger than that today. Consider a cache with 32 byte lines. The line number within a page would be determined bits 5 thru 11 of either the real or virtual address (counting rightmost bit as 0). For the cache to hold more than a page it might be “set associative” where there are be 2, 4 or 8 places for a given line to go, each with its own tag. It is possible that the line miss hardware algorithm could check the real addresses of each of the other tags in the set to notice aliasing. If the tag also holds the real address of each line, line write back performance would be improved.