Suppose that we have hardware with capability support.
Untrusted programs access memory with instructions that reference a memory capability and an offset.
This is a fairly conventional idea.
The (non capability) IBM 360 introduced an architecture that did not include data addresses in the instruction stream.
Given the popularity of Fortran with its array orientation most instructions that computed a memory address specified two general registers to whose sum was added a 12 bit offset found in the instruction.
When several arrays were accessed in a short span and those accesses involved the same subscript value, then then one of the registers could hold the origin of one array and the other register could hold the index.
I suspect that without the array orientation the following memory access patterns should suffice:<ul>
<li>capability register designation plus an offset from instruction.
<li>capability register designation plus an index found in some specified general register.
</ul>
If we have a real cache (tags hold DRAM addresses) then there are tricks we can use by exploiting the real nature of the descriptor registers.
We can use the Blaau trick for data by having one or two read addresses.
Th Plessey 250 taught that desciptor registers can keep seldom used values in memory (cache) where the hardware (or conceivably kernel code) can find it.
This works sell for the descriptor designating a control block.
It also works well as you step sequentially, or nearly sequentially, …
<p>Of course with capability access to memory we can use a virtual cache.