Flash memory is predicated on storing a bit by using a very small piece of metal, the floating gate, surrounded on all sides by insulator. An electric charge on this piece may last for years. The charge can be changed by sufficient voltage on a nearby conductor. Gradually such changes degrade the insulation and this limits how many time a ‘wirte-word’ in flash may be written. Reading flash is by sensing the electric field of the charge and reading is non destructive
There are two difficult tasks that are nearly alike:
Generational garbage collection results in blocks of storage that remain unmodified for significant time spans. I fear the consequences of stacking similar abstractions. Under common situations LRU upon LRU is pessimal instead of optimal. See this for other flash strategies.
I will try to record here the properties of NAND and NOR that are pertinent to the logical design. By “word” I mean the natural and efficient size of the unit of storing or of reading. The write-word may be bigger than the read-word. A large quoted read-word may imply a limitation on how often new addresses may be specified.
Both systems do split cycle big writes—erase followed by small ors-to-memory.
NOR writes are slow.
NOR provides fast reads and small read-words.
Jargon: The erase-word is conventionally called “erase segment”, “block” or “sector”.
The erase-word for NOR is large but the rewrite-word is small.
NAND is cheaper per bit than NOR.
The read-word for NAND is about 29 bits.