3D core arrays

This note describes the logic of the sort of ferrite core memory referred to as “X/Y line coincident-current” and described in the Wikipedia article but spelling out some aspects in more detail and others in less. Here we emphasize the coincidence word selection logic inherent in most core boxes of the 60’s and 70’s. The schemes below depend critically on a collection of magnetic cores so uniform, and a set of line-drivers sufficiently accurate that one unit of current, thru the core, repeated many times, reliably leaves the core unchanged, but two simultaneous units in the same direction reliably change the magnetic flux of the core according to the direction of the current. Simultaneous currents thru the core in opposite directions cancel their effect on the core. When a core’s flux changes it induces a voltage on lines thru it. If the current pushes the core toward state one, and the core is already in state one, there will be no flux change and no induced voltage. Ditto state zero. Here is some core physics.

In a memory box there is a ‘core stack’ which is a 3D array of cores. For a memory box with W bits per word and K words of memory, the array is W by X by Y where K = X×Y. Typically X=Y. There are X wires called x-lines, Y wires called y-lines and W wires called sense/inhibit lines (sense lines below). For every combination of one x-line, one y-line and one sense line, there is one core threaded by those three lines. Conversely every core is threaded by one x-line, one y-line and one sense line.

In a normal memory read operation the box receives a memory word address with sufficient information to select one X line and one Y line. The task is to deliver the W bits which are the current states of those cores selected by the address, and leave those cores in their previous states. In a normal memory write operation the box receives a word address and an additional W bits, and the task is to leave the selected cores in the states described by the additional bits.

Either of these two normal memory operations require two steps within the box. These steps were called ‘half cycles’ by some and ‘split cycles’ by others. For either task the first step is a destructive read where current is placed on one x-line and one y-line pushing each threaded core toward the zero state. Most cores will be threaded by neither of these two lines and will be unaffected. Some cores will be threaded by only one of these two lines but the current is carefully controlled so as to be insufficient to change the flux (state of magnetization) of such a core. W cores will be threaded by both lines and those two lines carry current thru the core in the same direction and these combined currents suffice to change the magnetic flux in the core. These W cores each have a distinct sense line thru it and if the core had been in a one state the changing flux induces a voltage on its own sense line. These sense lines each lead to a sense amplifier, and these amps capture the previous W core states. A core already in the zero state has no flux change and produces no signal on its sense line. The information detected by the sense amplifiers is captured in the regen register. The information in the cores, however, is destroyed; these W cores are left in the zero state by the destructive read.

The 2nd step, regeneration, is to replace information in the cores. For a read task this information is what was there before, and for a write task it is those W bits recently delivered to the box.

Again the same one x-line and one y-line are activated but with a reversed current pushing toward the one state. For most cores the sum of such currents is either zero or one unit and such cores are unchanged. Those W cores threaded by both energized lines would all be changed to state one except some of the sense lines are commandeered to selectively push, with one unit of current, towards zero thus leaving such triply selected cores in the zero state. Those bits which are selected by the x and y-lines but should be left in a zero state are threaded with two currents pushing towards one, and a sense line with current pushing towards zero; they remain in the zero state.

2D core arrays

The corresponding logic for 2D arrays is much simpler—for sensing there is no upper current limit to be observed. In 2D there is one word line per word and that line is pulsed to read the data. Information flows out on as many sense lines as there are bits in a word. For regeneration, the word line is pulsed again in the opposite direction, and a canceling current in selected sense lines thwarts setting all the bits. This design requires a line and driver per memory word and is this usually more expensive.

For either 2D or 3D core stacks, these tricks exploit other uses of the fundamental steps described above.

See this for an entirely mechanical 2D binary writable memory that preceded core memory.

This describes how modern SDRAM is like 2D core and some flakey products in the field.